: The PC places the address on the bus; ALE latches it. The processor fetches 2Bh . In T4cap T sub 4
To visualize the diagram, consider the following behavior of the system bus during these 16 T-states:
: The processor places the 16-bit address it just "learned" onto the address bus. It reads the byte at that location and stores it in the L register .
: The processor reads the two-byte address from the memory locations immediately following the opcode.
Uses the 16-bit address just loaded to read data into the . M5 Memory Read 3 T-states
Increments the address by 1 and reads data into the . 3. Signal Behavior in the Timing Diagram
: The PC places the address on the bus; ALE latches it. The processor fetches 2Bh . In T4cap T sub 4
To visualize the diagram, consider the following behavior of the system bus during these 16 T-states:
: The processor places the 16-bit address it just "learned" onto the address bus. It reads the byte at that location and stores it in the L register .
: The processor reads the two-byte address from the memory locations immediately following the opcode.
Uses the 16-bit address just loaded to read data into the . M5 Memory Read 3 T-states
Increments the address by 1 and reads data into the . 3. Signal Behavior in the Timing Diagram